A High Speed and Low Power 4-Bit Multiplier using FinFET Technology

被引：0

作者：

Bathla, Shikha ^{[1
]}

Purohit, Nidhi ^{[1
]}

机构：

[1] Amity Univ, ASET, Dept ECE, Noida, India

来源：

PROCEEDINGS ON 2016 2ND INTERNATIONAL CONFERENCE ON NEXT GENERATION COMPUTING TECHNOLOGIES (NGCT) | 2016年

关键词：

FinFET; IG/LP; sleep mode; tri mode;

D O I：

暂无

中图分类号：

TP39 [计算机的应用];

学科分类号：

081203 ; 0835 ;

摘要：

In this paper a High Speed and Low Power 4-Bit Multiplier using FinFET technology at 32nm is proposed. Comparative analysis of MOSFET based and FinFET based multiplier is done using HSPICE tool. FinFET is found to be less power consuming than MOSFET by 97%. Further optimization of FinFET based multiplier is achieved in terms of delay using sleep mode and tri mode techniques by 28% and 81% respectively.

引用

页码：61 / 64

页数：4

共 7 条

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