A Single-Channel 5bit 333MS/s Asynchronous Digital Slope ADC Based on CMOS Technology

被引：0

作者：

Shu, Yujun ^{[1
]}

Mei, Fengyi ^{[1
]}

Yu, Youling ^{[1
]}

机构：

[1] Tong Univ, Sch Elect & Informat Engn, Shanghai, Peoples R China

来源：

2017 3RD IEEE INTERNATIONAL CONFERENCE ON COMPUTATIONAL INTELLIGENCE & COMMUNICATION TECHNOLOGY (CICT) | 2017年

关键词：

asynchronous; digital slope; self-disabled; CMOS; delay cells;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

This project design and present a 5-bit 333MS/s digital slope ADC (analog-to-digital converter. It is implemented and simulated with Cadence tool in SMIC 55nm CMOS technology. The power supply is 1.2 V and the improved delay cells are used which can shorten the delay time to 50ps. In addition, a self-disabled comparator is used to save power. When the peak-to-peak value of input is 0.4V, the SNDR(Signal to Noise and Distortion Ratio) is 28.19 dB, ENOB(Effective Number of Bits) is 4.39 bit, SFDR(Spurious Free Dynamic Range) is 35.87 dB, SNR(Signal-to-Noise Ratio) is 31.47dB.

引用

页数：4

共 6 条

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[3] A 0.8-mW 5-bit 250-MS/s Time-Interleaved Asynchronous Digital Slope ADC
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Zhou, Cui
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[5] Verbruggen Bob, 2010, 2010 IEEE International Solid-State Circuits Conference (ISSCC), P296, DOI 10.1109/ISSCC.2010.5433925
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