Silicon clean impact on 90nm CMOS devices performance

被引：3

作者：

Carrère, JP ^{[1
]}

Bernard, H ^{[1
]}

Petitdidier, S ^{[1
]}

Beverina, A ^{[1
]}

Rosa, J ^{[1
]}

Guyader, F ^{[1
]}

机构：

[1] ST Microelect, Crolles, France

来源：

ESSDERC 2003: PROCEEDINGS OF THE 33RD EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE | 2003年

关键词：

D O I：

10.1109/ESSDERC.2003.1256857

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We show in this paper that 90nm NMOS performance can be enhanced by minimizing the silicon consumption due to the wet cleaning processes of the Double Gate Oxide module. A complete analysis is presented showing a good correlation between the increase of the electrons mobility and the reduction of the silicon clean consumption. We also discuss why the PMOS behavior is not altered by these cleans. Moreover, a 4% delay reduction on ring oscillators is measured. Finally, both the thick and thin gate oxide quality has been preserved: this shows that an ideal compromise has been found between the silicon cleaning efficiency and the devices performance improvement.

引用

页码：235 / 238

页数：4