Phase noise in frequency divider circuits

被引：10

作者：

Apostolidou, Melina ^{[1
]}

Baltus, Peter G. M. ^{[2
]}

Vaucher, Cicero S. ^{[1
]}

机构：

[1] NXP Semicond, HTC 37, NL-5656 AE Eindhoven, Netherlands

[2] Tech Univ Eindhoven, NL-5600MB Eindhoven, Netherlands

来源：

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年

关键词：

D O I：

10.1109/ISCAS.2008.4541973

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We identify limitations of the models for phase noise in frequency dividers by Egan and by Phillips and present a new model applicable to both high frequency and low power frequency divider design. Further, we design both synchronous and asynchronous frequency divider test chips that allow us to observe experimentally the effects of noise accumulation, Sampling frequency and biasing conditions on the total phase noise performance of frequency dividers. We use our measurements to validate the simulated values obtained by time domain phase noise analysis offered by the commercial simulator Spectre RE The measured data show good agreement with the simulation results.

引用

页码：2538 / +

页数：2

共 4 条

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[2] Phase noise in digital frequency dividers [J].

Levantino, S ;

Romanò, L ;

Pellerano, S ;

Samori, C ;

Lacaita, AL .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (05) :775-784

[3]

Phillips D.E., 1987, IEEE 41 ANN FREQ CON, P507

[4] A low-power 20 GHz static frequency divider with programmable input sensitivity [J].

Vaucher, CS ;

Apostolidou, M .

2002 IEEE RADIO FREQUENCY INTEGRATED CIRCUITS (RFIC) SYMPOSIUM, DIGEST OF PAPERS, 2002, :235-238

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