A low-power bootstrapped CMOS full adder

被引：7

作者：

Hernández, MA ^{[1
]}

Aranda, ML ^{[1
]}

机构：

[1] INAOA, Dept Elect, Puebla, Mexico

来源：

2005 2ND INTERNATIONAL CONFERENCE ON ELECTRICAL & ELECTRONICS ENGINEERING (ICEEE) | 2005年

关键词：

bootstrap; full adder; low-power; XOR-XNOR;

D O I：

10.1109/ICEEE.2005.1529618

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a CMOS full adder built upon bootstrapped pass transistor logic is presented. With the characteristics of full voltage swing at internal nodes and very low short circuit current, HSPICE and Nanosim simulations shown that the proposed full adder offers a power-delay improvement of 36% over the best of other I-bit full adders that were compared. A 0.35 mu m CMOS technology and a power Supply of 3.3.V were used to simulate these adders. When used to build an 8-bits carry-ripple adder, the proposed full adder offers power savings up to 28% respect to the other ones.

引用

页码：243 / 246

页数：4

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