A 10-Bit 600-MS/s Time-Interleaved SAR ADC With Interpolation-Based Timing Skew Calibration

被引：43

作者：

Li, Dengquan ^{[1
]}

Zhu, Zhangming ^{[1
]}

Ding, Ruixue ^{[1
]}

Liu, Maliang ^{[1
]}

Yang, Yintang ^{[1
]}

Sun, Nan ^{[2
]}

机构：

[1] Xidian Univ, Sch Microelect, Shaanxi Key Lab Integrated Circuits & Syst, Xian 710071, Shaanxi, Peoples R China

[2] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2019年 / 66卷 / 01期

基金：

中国国家自然科学基金;

关键词：

Successive approximation register ADC; time-interleaved (TI); timing skew calibration; finite-impulse response (FIR) filter; reference voltage generator; ALL-DIGITAL CALIBRATION;

D O I：

10.1109/TCSII.2018.2828649

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This brief presents a 10-bit 600 MS/s 4-channel time-interleaved (TI) successive approximation register analog-to-digital converter (ADC). A background calibration algorithm using Lagrange polynomial interpolation is introduced to calibrate timing skew. It consists of digital detection and adaptive derivative-based correction, employing low filter taps and resulting in hardware reduction. Two reference voltage generators are implemented on-chip to provide a stable reference voltage for the sub-ADCs, enhancing the reliability and robustness of the circuits. The TI-ADC prototype is fabricated in the 65-nm CMOS process and occupies an area of 0.69 mm(2). The measurement results show that at a sampling rate of 600 MS/s the ADC achieves a 49-dB SNDR after calibration while dissipating 34 mW from a 1.2/2.5-V supply.

引用

页码：16 / 20

页数：5

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