A 40-Gb/s clock and data recovery circuit in 0.18-μm CMOS technology

被引：94

作者：

Lee, J ^{[1
]}

Razavi, B ^{[1
]}

机构：

[1] Univ Calif Los Angeles, Dept Elect Engn, Los Angeles, CA 90095 USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2003年 / 38卷 / 12期

关键词：

CDR circuits; demultiplexers; injection locking; oscillators; phase detectors; phase-locked loops;

D O I：

10.1109/JSSC.2003.818566

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A phase-locked clock and data recovery circuit incorporates a multiphase LC oscillator and a quarter-rate bang-bang phase detector. The oscillator is based on differential excitation of a closed-loop transmission line at evenly spaced points, providing half-quadrature phases. The phase detector employs eight flip-flops to sample the input every 12.5 ps, detecting data transitions while retiming and demultiplexing the data into four 10-Gb/s outputs. Fabricated in 0.18-mum CMOS technology, the circuit produces a clock jitter of 0.9 ps(rms) and 9.67 ps(pp) with a PRBS of 2(31)-1 while consuming 144 mW from a 2-V supply.

引用

页码：2181 / 2190

页数：10

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