Hardware-Software Co-Design for Efficient and Scalable Real-Time Emulation of SNNs on the Edge

被引：5

作者：

Angel Oltra-Oltra, Josep ^{[1
]}

Madrenas, Jordi ^{[1
]}

Zapata, Mireya ^{[2
]}

Vallejo, Bernardo ^{[1
]}

Mata-Hernandez, Diana ^{[1
]}

Sato, Shigeo ^{[3
]}

机构：

[1] Univ Politecn Cataluna, Dept Elect Engn, Barcelona, Spain

[2] Univ Tecnol Indoamer, Res Ctr Mechatron & Interact Syst, Quito, Ecuador

[3] Tohoku Univ, Res Inst Elect Commun, Sendai, Miyagi, Japan

来源：

2021 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2021年

关键词：

Spiking Neural Networks; SNN; Edge Computing; Neural Computing; Hardware-Software Integration; SNAVA; HEENS;

D O I：

10.1109/ISCAS51556.2021.9401615

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper introduces a novel workflow for Distributed Spiking Neural Network Architecture (DSNA). As such, the hardware implementation of Single Instruction Multiple Data (SIMD)-based Spiking Neural Network (SNN) requires the development of user-friendly and efficient toolchain in order to maximise the potential that the architecture brings. By using a novel SNN architecture, a custom designed hardware/software toolchain has been developed. The toolchain performance has been experimentally checked on a Band-Pass Filter (BPF), obtaining optimized code and data.

引用

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