An Experimental Study of Phase Noise in CMOS Phase-Locked Loops Considering Different Noise Sources

The loop model of a second order phase-locked loop (PLL) is presented. The effects of different building blocks on the phase noise performance of PLLs are analyzed. Input reference clock, voltage-con trolled oscillator (VCO) and the frequency divider are the dominant noise sources in a PILL system. PLL phase noise prediction by the graphical treatment is introduced. Different types of VCOs are fabricated in 0.5(mu m) CMOS process to investigate the open loop VCO noise. PLLs with different VCOs are also fabricated to study the effect of VCO noise, input reference noise and the divider noise on the noise performance of the whole PLL system. Experimental results closely follow the predicted performance.