A High-Performance Symmetric Hybrid Form Design for High-Order FIR Filters

被引:0
作者
Ye, Jinghao [1 ]
Yanagisawa, Masao [1 ]
Shi, Youhua [1 ]
机构
[1] Waseda Univ, Grad Sch Fundamental Sci & Engn, Tokyo 1698555, Japan
来源
APCCAS 2020: PROCEEDINGS OF THE 2020 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2020) | 2020年
关键词
FIR filter; symmetric hybrid FIR; EFFICIENT REALIZATION; LOW-POWER;
D O I
10.1109/apccas50809.2020.9301685
中图分类号
TP18 [人工智能理论];
学科分类号
081104 ; 0812 ; 0835 ; 1405 ;
摘要
In this paper, a symmetric hybrid form for high performance finite impulse response (FIR) filters with symmetric coefficients is proposed, which can be utilized in both fixed and reconfigurable FIR implementations to solve the driving capacity problem caused by the high fanout signals in the existing symmetric transposed form based FIR architecture. The evaluation results show that, when compared with the existing high speed FIR designs such as the symmetric systolic form in [13] and the hybrid form in [1], the proposed form can achieve significant area and power savings with great ADP and PDP reduction. Moreover, when compared with the symmetric systolic form in [13] the required latency can be approximately reduced by 33.3%, which clearly shows the performance improvement of the proposed method.
引用
收藏
页码:121 / 124
页数:4
相关论文
共 13 条
[1]  
Abdel-Raheem E., 1993, 1993 Canadian Conference on Electrical and Computer Engineering (Cat. No.93TH0590-0), P680, DOI 10.1109/CCECE.1993.332387
[2]   Low-power equalizer architectures for high-speed modems [J].
Azadet, K ;
Nicole, CJ .
IEEE COMMUNICATIONS MAGAZINE, 1998, 36 (10) :118-126
[3]  
Kei-Yong Khoo, 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196), P621, DOI 10.1109/ISCAS.2001.921147
[4]  
Kovalev A, 2017, CONF REC ASILOMAR C, P1779, DOI 10.1109/ACSSC.2017.8335667
[5]   SYSTOLIC REALIZATION OF LINEAR PHASE FIR DIGITAL FILTERS. [J].
Kwan, Hon Keung .
IEEE transactions on circuits and systems, 1987, CAS-34 (12) :1604-1605
[6]   Fine-Grained Critical Path Analysis and Optimization for Area-Time Efficient Realization of Multiple [J].
Lou, Xin ;
Yu, Ya Jun ;
Meher, Pramod Kumar .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2015, 62 (03) :863-872
[7]   Memory Footprint Reduction for Power-Efficient Realization of 2-D Finite Impulse Response Filters [J].
Mohanty, Basant K. ;
Meher, Pramod K. ;
Al-Maadeed, Somaya ;
Amira, Abbes .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2014, 61 (01) :120-133
[8]   A High-Performance FIR Filter Architecture for Fixed and Reconfigurable Applications [J].
Mohanty, Basant Kumar ;
Meher, Pramod Kumar .
IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2016, 24 (02) :444-452
[9]   PIPELINE INTERLEAVING AND PARALLELISM IN RECURSIVE DIGITAL-FILTERS .1. PIPELINING USING SCATTERED LOOK-AHEAD AND DECOMPOSITION [J].
PARHI, KK ;
MESSERSCHMITT, DG .
IEEE TRANSACTIONS ON ACOUSTICS SPEECH AND SIGNAL PROCESSING, 1989, 37 (07) :1099-1117
[10]   Computation sharing programmable FIR filter for low-power and high-performance applications [J].
Park, J ;
Jeong, W ;
Mahmoodi-Meimand, H ;
Wang, YT ;
Choo, H ;
Roy, K .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (02) :348-357