n-Channel MOSFETs Fabricated on SiGe Dots for Strain-Enhanced Mobility

被引:38
作者
Jovanovic, V. [1 ]
Biasotto, C. [1 ]
Nanver, L. K. [1 ]
Moers, J. [2 ]
Gruetzmacher, D. [2 ]
Gerharz, J. [2 ]
Mussler, G. [2 ]
van der Cingel, J. [1 ]
Zhang, J. J. [3 ]
Bauer, G. [3 ]
Schmidt, O. G. [4 ]
Miglio, L. [5 ]
机构
[1] Delft Univ Technol, Delft Inst Microsyst & Nanoelect, NL-2628 Delft, Netherlands
[2] Forschungszentrum Julich, D-52428 Julich, Germany
[3] Johannes Kepler Univ Linz, A-4040 Linz, Austria
[4] IFW Dresden, Inst Integrat Nanosci, D-01069 Dresden, Germany
[5] Univ Milano Bicocca, I-20126 Milan, Italy
关键词
CMOS; excimer-laser annealing (ELA); low-temperature gate stack; SiGe; strain-enhanced mobility; Stranski-Krastanow (S-K) growth mode; ultrashallow source/drain junctions; DEVICES;
D O I
10.1109/LED.2010.2058995
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The silicon germanium dots grown in the Stranski-Krastanow mode are used to induce biaxial tensile strain in a silicon capping layer. A high Ge content and correspondingly high Si strain levels are reached due to the 3-D growth of the dots. The n-channel MOS devices, referred to in this letter as DotFETs, are processed with the main gate segment above the strained Si layer on a single dot. To prevent the intermixing of the Si/SiGe/Si structure, a novel low-temperature FET structure processed below 400 degrees C has been implemented: The ultrashallow source/drain junctions formed by excimer-laser annealing in the full-melt mode of ion-implanted dopants are self-aligned to a metal gate. The crystallinity of the structure is preserved throughout the processing, and compared to reference devices, an average increase in the drain current of up to 22.5% is obtained.
引用
收藏
页码:1083 / 1085
页数:3
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