A New MAC Design Using High-Speed Partial Product Summation Tree

被引：0
|
作者：
Asadee, P. [1 ]
机构：
[1] Islamic Azad Univ, Varamin Pishva Branch, Tehran, Iran
来源：
2009 2ND IEEE INTERNATIONAL CONFERENCE ON COMPUTER SCIENCE AND INFORMATION TECHNOLOGY, VOL 3 | 2009年
关键词：
adder; arithmetic; CMOS; counter; VLSI; MULTIPLIERS;
D O I：
10.1109/ICCSIT.2009.5234712
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
A novel multiplication algorithm using high-speed partial product summation tree has been presented. Some changes have been done in previous algorithms to obtain speed and better electronic parameters. In partial product generation step a new modified Booth algorithm has been proposed. In partial product reduction step a novel tree structure has been modified. In final addition step a fast adder structure using high-speed components is used. The modified Booth structure decreases the delay with the production of partial products by using the additional parallelism of conventional Booth algorithm. Multiplication is partitioned in four slices which results more speed. A new carry save addition has been used in final addition step. Modified high-speed array architecture is proposed. Simulations have been done with SPICE and some programming codes. This study has decreased transistor count by 8 percent, delay time of whole architecture has reduced 10 percent and power consumption reduction is 10 percent in compare with other previous designs.
引用
收藏
页码：231 / 234
页数：4
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