A V-Band MMIC Doubler Using a 4th Harmonic Mixing Technique

A V-band frequency doubler consisting of a harmonics generating stage and a mixing-amplifying stage is proposed. In the first stage, a common source-common gate (CS-CG) topology is deployed to attenuate the odd order harmonics. A common source transistor is implemented in the second stage to amplify the 2nd harmonic and down convert the fourth harmonic to the desired second harmonic frequency. This transistor is biased in the nonlinear regime. The in-phase addition of 2nd harmonics generated by amplifying and mixing mechanisms improves the overall conversion gain and power added efficiency (PAE) of the doubler. A proof-of-concept circuit is designed and manufactured in a 0.1-mu m GaAs pHEMT technology. The proposed doubler demonstrates up to 35 dBc rejection ratio of undesired harmonics while it shows a conversion gain of 9.2 dB. The doubler consumes dc power of 146 mW and achieves a peak PAE of 20%.