MorphoSys: A reconfigurable architecture for multimedia applications

被引：12

作者：

Singh, H ^{[1
]}

Lee, MH ^{[1
]}

Lu, GM ^{[1
]}

Kurdahi, FJ ^{[1
]}

Bagherzadeh, N ^{[1
]}

机构：

[1] Univ Calif Irvine, Irvine, CA 92717 USA

来源：

XI BRAZILIAN SYMPOSIUM ON INTEGRATED CIRCUIT DESIGN, PROCEEDINGS | 1998年

关键词：

D O I：

10.1109/SBCCI.1998.715427

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We describe the MorphoSys I reconfigurable system, which combines a reconfigurable array of processor cells with a RISC processor core and a high bandwidth memory interface unit. We introduce the array architecture, its configuration memory, inter-connection network, role of the control processor and related components. Architecture implementation is described in brief and the efficacy of MorphoSys is demonstrated through simulation of video compression (MPEG-2) and target-recognition applications. Comparison with other implementations illustrates that MorphoSys achieves higher performance by up to 10X.

引用

页码：134 / 139

页数：6

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