An efficient architecture of 8-bit CMOS analog-to-digital converter

被引：3

作者：

Tan, PBY ^{[1
]}

Suparjo, BS ^{[1
]}

Wagiran, R ^{[1
]}

Sidek, R ^{[1
]}

机构：

[1] Univ Pertanian Malaysia, Fac Engn, Dept Elect & Elect Engn, Serdang 43400, Malaysia

来源：

2000 IEEE INTERNATIONAL CONFERENCE ON SEMICONDUCTOR ELECTRONICS, PROCEEDINGS | 2000年

关键词：

D O I：

10.1109/SMELEC.2000.932459

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An 8-bit CMOS analog-to-digital converter (ADC) has been designed using a more efficient architecture. The simplified multistep 8-bit ADC requires two 4-bit full-flash cycles by using a modified 4-bit full-flash ADC with a voltage estimator. The speed of this new architecture is similar to conventional half-flash ADC but the die area consumption is much less due to reduced numbers of comparators and resistors.

引用

页码：178 / 186

页数：9