Effects of Scaling on Muon-Induced Soft Errors

被引：0

作者：

Sierawski, Brian D. ^{[1
]}

Reed, Robert A. ^{[1
]}

Mendenhall, Marcus H. ^{[1
]}

Weller, Robert A. ^{[1
]}

Schrimpf, Ronald D. ^{[1
]}

Wen, Shi-Jie ^{[2
]}

Wong, Richard ^{[2
]}

Tam, Nelson ^{[3
]}

Baumann, Robert C. ^{[4
]}

机构：

[1] Vanderbilt Univ, Inst Space & Def Elect, Nashville, TN 37212 USA

[2] Cisco Syst Inc, San Jose, CA 95134 USA

[3] Marvell Semicond Inc, Santa Clara, CA 95054 USA

[4] Text Inst, Dallas, TX 75243 USA

来源：

2011 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS) | 2011年

关键词：

SINGLE-EVENT-UPSETS; MODEL;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Experimental results are presented that indicate technology scaling increases the sensitivity of microelectronics to soft errors from low-energy muons. Results are presented for 65, 55, 45, and 40 nm bulk CMOS SRAM test arrays. Simulations suggest an increasing role of muons in the soft error rate for smaller technologies.

引用

页数：6

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