Viterbi decoding on a co-processor architecture with vector parallelism

A programmable co-processor architecture combining VLIW and vector parallelism has been introduced in [1]. In this paper, the mapping of Viterbi decoding algorithm on this architecture is presented. Initially, algorithm analysis and vectorizing transformations are discussed. The resulting vectorized algorithm is used for defining two generic vector instructions for Viterbi decoding. These are the 'add-compare-select' (ACS) and manhattan distance (MANH) instructions. The design of these instructions is presented and their genericity is demonstrated by discussing how various Viterbi decoder instances (such as Wary Viterbi and Viterbi decoding for blind transport format detection) can be implemented using CVP Viterbi instructions. Finally, the throughput estimations of two binary Viterbi decoder implementations (UMTS and GSM) are benchmarked against a number of existing processors. The results present a higher throughput than comparable architectures, demonstrating that a good tradeoff has been achieved between instruction set flexibility and decoding throughput.