Time-Multiplexed Online Checking

被引:9
作者
Gao, Ming [1 ]
Chang, Hsiu-Ming [1 ]
Lisherness, Peter
Cheng, Kwang-Ting [2 ,3 ]
机构
[1] Univ Calif Santa Barbara, Dept Elect & Comp Engn, SoC Design & Test Lab, Santa Barbara, CA 93106 USA
[2] Univ Calif Santa Barbara, Comp Engn Program, Santa Barbara, CA 93106 USA
[3] Univ Calif Santa Barbara, ECE Dept, Santa Barbara, CA 93106 USA
关键词
Availability; built-in tests; error-checking; fault tolerance; DESIGN; LOGIC;
D O I
10.1109/TC.2011.34
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
There is a growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, their area overhead remains too high for cost-sensitive applications. In this paper, we introduce a Time-Multiplexed Online Checking (TMOC) scheme using embedded field-programmable blocks for checker implementation, which enables various system parts to be checked dynamically in-field in a time-multiplexed fashion. The test quality analyses using a probabilistic model show that TMOC could maintain high fault coverage that is similar to traditional dedicated checkers. We conducted a case study of an H. 264 decoder design that demonstrates our TMOC scheme provides a significant reduction in chip area and power overhead for online checkers at the cost of increased fault detection latency. We have successfully implemented and demonstrated our proposed TMOC scheme using a single Field-Programmable Gate Array (FPGA) chip.
引用
收藏
页码:1300 / 1312
页数:13
相关论文
共 36 条
[21]  
Gao M, 2010, INT HIGH LEVEL DESIG, P90, DOI 10.1109/HLDVT.2010.5496657
[22]   Time-Multiplexed Online Checking: A Feasibility Study [J].
Gao, Ming ;
Chang, Hsiu-Ming ;
Lisherness, Peter ;
Cheng, Kwang-Ting .
PROCEEDINGS OF THE 17TH ASIAN TEST SYMPOSIUM, 2008, :371-376
[23]   Test for detection & location of intermittent faults in combinational circuits [J].
Ismaeel, AA ;
Bhatnagar, R .
IEEE TRANSACTIONS ON RELIABILITY, 1997, 46 (02) :269-274
[24]   Heterogeneous redundancy for fault and defect tolerance with complexity independent area overhead [J].
Kumar, VV ;
Lach, J .
18TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 2003, :571-578
[25]   ARCHITECTURAL PRINCIPLES FOR SAFETY-CRITICAL REAL-TIME APPLICATIONS [J].
LALA, JH ;
HARPER, RE .
PROCEEDINGS OF THE IEEE, 1994, 82 (01) :25-40
[26]   DESIGN TECHNIQUES FOR TESTABLE EMBEDDED ERROR CHECKERS [J].
MCCLUSKEY, EJ .
COMPUTER, 1990, 23 (07) :84-88
[27]   Function-Inherent Code checking:: A new low cost on-line testing approach for high performance microprocessor control logic [J].
Metra, C. ;
Rossi, D. ;
Omana, M. ;
Jas, A. ;
Galivanche, R. .
PROCEEDINGS OF THE 13TH IEEE EUROPEAN TEST SYMPOSIUM: ETS 2008, 2008, :171-+
[28]   Reconfigurable architecture for autonomous self-repair [J].
Mitra, S ;
Huang, WJ ;
Saxena, NR ;
Yu, SY ;
McCluskey, EJ .
IEEE DESIGN & TEST OF COMPUTERS, 2004, 21 (03) :228-240
[29]   Which concurrent error detection scheme to choose? [J].
Mitra, S ;
McCluskey, EJ .
INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, :985-994
[30]  
Shamshiri S., 2008, PROC IEEE INT TEST C, P1