Time-Multiplexed Online Checking

被引:8
作者
Gao, Ming [1 ]
Chang, Hsiu-Ming [1 ]
Lisherness, Peter
Cheng, Kwang-Ting [2 ,3 ]
机构
[1] Univ Calif Santa Barbara, Dept Elect & Comp Engn, SoC Design & Test Lab, Santa Barbara, CA 93106 USA
[2] Univ Calif Santa Barbara, Comp Engn Program, Santa Barbara, CA 93106 USA
[3] Univ Calif Santa Barbara, ECE Dept, Santa Barbara, CA 93106 USA
关键词
Availability; built-in tests; error-checking; fault tolerance; DESIGN; LOGIC;
D O I
10.1109/TC.2011.34
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
There is a growing demand for online hardware checking capability to cope with increasing in-field failures resulting from variability and reliability problems. While many online checking schemes have been proposed, their area overhead remains too high for cost-sensitive applications. In this paper, we introduce a Time-Multiplexed Online Checking (TMOC) scheme using embedded field-programmable blocks for checker implementation, which enables various system parts to be checked dynamically in-field in a time-multiplexed fashion. The test quality analyses using a probabilistic model show that TMOC could maintain high fault coverage that is similar to traditional dedicated checkers. We conducted a case study of an H. 264 decoder design that demonstrates our TMOC scheme provides a significant reduction in chip area and power overhead for online checkers at the cost of increased fault detection latency. We have successfully implemented and demonstrated our proposed TMOC scheme using a single Field-Programmable Gate Array (FPGA) chip.
引用
收藏
页码:1300 / 1312
页数:13
相关论文
共 36 条
  • [1] [Anonymous], P INT S PHYS DES ISP
  • [2] [Anonymous], P IEEE INT S CIRC SY
  • [3] [Anonymous], P 15 INT S IEEE FIEL
  • [4] [Anonymous], XBOX 360 FAILURE RAT
  • [5] [Anonymous], P 44 ANN C DES AUT D
  • [6] [Anonymous], P IEEE INT TEST C
  • [7] [Anonymous], P 45 ANN C DES AUT D
  • [8] [Anonymous], NEW APPROACH IN SYST
  • [9] [Anonymous], MENTA EFPGA COR 2 DA
  • [10] [Anonymous], P IEEE INT TEST C