Energy-Efficient Advanced Data Encryption System Using Spin-Based Computing-in-Memory Architecture

被引:12
作者
Nisar, Arshid [1 ]
Dhull, Seema [1 ]
Shreya, Sonal [2 ]
Kaushik, Brajesh Kumar [1 ]
机构
[1] Indian Inst Technol Roorkee, Dept Elect & Commun, Roorkee 247667, Uttarakhand, India
[2] Aarhus Univ, Dept Elect & Comp Engn Elect & Photon, DK-8000 Aarhus, Denmark
关键词
Computer architecture; Encryption; Switches; Magnetization; Performance evaluation; Voltage control; Spintronics; Advanced encryption standard (AES); computing-in-memory (CiM); spintronics; voltage-controlled SOT;
D O I
10.1109/TED.2022.3150623
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Spintronic-based computing-in-memory (CiM) architecture has emerged as one of the efficient solutions to eliminate the latency/bandwidth bottleneck of conventional von-Neumann architecture. Voltage-controlled spin-orbit torque (SOT) memory offers ultralow power and high-speed operation among the various spintronic memories. In this article, advanced encryption standard (AES) system within CiM architecture using voltage-controlled SOT device has been presented. The entire encryption process is performed within the high-density spintronic-based memory array to achieve low power and high processing speed. The reconfigurable logic operations and random key generation for AES are achieved by using a single voltage-controlled SOT device within the memory array. The results show that the proposed architecture is 96%, 52.1%, and 14% more efficient in terms of energy consumption, throughput, and area, respectively, when compared with one of the most efficient SOT-based AES systems.
引用
收藏
页码:1736 / 1742
页数:7
相关论文
共 21 条
[1]   Efficient CMOL Gate Designs for Cryptography Applications [J].
Abid, Z. ;
Alma'aitah, A. ;
Barua, M. ;
Wang, W. .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2009, 8 (03) :315-321
[2]   Design and Evaluation of a Spintronic In-Memory Processing Platform for Nonvolatile Data Encryption [J].
Angizi, Shaahin ;
He, Zhezhi ;
Bagherzadeh, Nader ;
Fan, Deliang .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2018, 37 (09) :1788-1801
[3]   Spintronics based random access memory: a review [J].
Bhatti, Sabpreet ;
Sbiaa, Rachid ;
Hirohata, Atsufumi ;
Ohno, Hideo ;
Fukami, Shunsuke ;
Piramanayagam, S. N. .
MATERIALS TODAY, 2017, 20 (09) :530-548
[4]   Prospect of Spin-Orbitronic Devices and Their Applications [J].
Cao, Yi ;
Xing, Guozhong ;
Lin, Huai ;
Zhang, Nan ;
Zheng, Houzhi ;
Wang, Kaiyou .
ISCIENCE, 2020, 23 (10)
[5]   PRIME: A Novel Processing-in-memory Architecture for Neural Network Computation in ReRAM-based Main Memory [J].
Chi, Ping ;
Li, Shuangchen ;
Xu, Cong ;
Zhang, Tao ;
Zhao, Jishen ;
Liu, Yongpan ;
Wang, Yu ;
Xie, Yuan .
2016 ACM/IEEE 43RD ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE (ISCA), 2016, :27-39
[6]   Modeling and Exploration of the Voltage-Controlled Magnetic Anisotropy Effect for the Next-Generation Low-Power and High-Speed MRAM Applications [J].
Kang, Wang ;
Ran, Yi ;
Zhang, Youguang ;
Lv, Weifeng ;
Zhao, Weisheng .
IEEE TRANSACTIONS ON NANOTECHNOLOGY, 2017, 16 (03) :387-395
[7]   Spin-Orbit-Torque-Based Spin-Dice: A True Random-Number Generator [J].
Kim, Yusung ;
Fong, Xuanyao ;
Roy, Kaushik .
IEEE MAGNETICS LETTERS, 2015, 6
[8]   Design of high-throughput and low-power true random number generator utilizing perpendicularly magnetized voltage-controlled magnetic tunnel junction [J].
Lee, Hochul ;
Ebrahimi, Farbod ;
Amiri, Pedram Khalili ;
Wang, Kang L. .
AIP ADVANCES, 2017, 7 (05)
[9]   340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(24)2 Polynomials in 22 nm Tri-Gate CMOS [J].
Mathew, Sanu ;
Satpathy, Sudhir ;
Suresh, Vikram ;
Anders, Mark ;
Kaul, Himanshu ;
Agarwal, Amit ;
Hsu, Steven ;
Chen, Gregory ;
Krishnamurthy, Ram .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2015, 50 (04) :1048-1058
[10]  
Parveen F., 2017, 2017 IEEE/ACM International Symposium on Low Power Electronics and Design, P1, DOI DOI 10.1109/ISLPED.2017.8009200