Design Optimization and Analysis of Multicontext STT-MTJ/CMOS Logic Circuits

High power issues have become the main drawbacks of CMOS logic circuits as technology node shrinks below 45 nm. Emerging spintronics nanodevices-based hybrid logic-in-memory architecture has recently been investigated to overcome these issues. Among them, spin-transfer-torque-based magnetic tunnel junction (STT-MTJ) nanopillar is one of the most promising spintronics nanodevices thanks to its nonvolatility, fast access speed, and 3-D integration with CMOS technology. However, hybrid STT-MTJ/CMOS logic faces severe reliability issues in ultradeep submicron technology nodes (e.g., 28 nm) due to the increasing process variations and reduced supply voltage. This paper presents architecture designs and comparative study of multicontext hybrid STT-MTJ/CMOS logic structures with a particular focus on reliability investigation. Their merits and shortcomings are demonstrated depending on the addressed applications. Finally, some design considerations and strategies are also presented to further optimize their reliability performance. Transient and Monte Carlo statistical analyses are performed by using an industrial CMOS 28-nm design kit and a physics-based STT-MTJ nanopillar compact model to exhibit their functionalities and effectiveness.