Single metal/dual high-k gate stack with low Vth and precise gate profile control for highly manufacturable aggressively scaled CMISFETs

被引：25

作者：

Mise, N. ^{[1
]}

Morooka, T. ^{[1
]}

Eimori, T. ^{[1
]}

Kamiyarna, S. ^{[1
]}

Murayama, K. ^{[2
,3
]}

Sato, M. ^{[1
]}

Ono, T. ^{[1
]}

Nara, Y. ^{[1
]}

Ohji, Y. ^{[1
]}

机构：

[1] Semicond Leading Edge Technol Inc, 16-1 Onogawa, Tsukuba, Ibaraki, Japan

[2] Assoc Superadv Elect Technol, Nagoya, Aichi, Japan

[3] Hitachi Kenki FineTech Co Ltd, Bunkyo, Japan

来源：

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/IEDM.2007.4418991

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

We have proposed a single metal/dual high-k (SMDH), low-V-th gate stack for aggressively scaled CMISFETs. The V-th is controlled by MgO- and Al2O3-containing high-k for n and pMISFETs, respectively The gate profile can be more easily controlled by taking advantage of a common W/TiN gate stack on both high-k's. We have successfully obtained 0.21 and -0.33 V o V-th for a 1-mu m long n and pMISFET by the proposed SMDH gate stacks. We also found that MgO suppresses PBTI and that it enhances electron mobility.

引用

页码：527 / +

页数：2

共 50 条

[21] Improved gate-edge profile of metal/high-k gate stack using an NH3 ashing process in gate-first CMOSFETs [J].

Song, SC ;

Zhang, Z ;

Huffman, C ;

Bae, SH ;

Sim, JH ;

Lee, BH .

ELECTROCHEMICAL AND SOLID STATE LETTERS, 2006, 9 (01) :G4-G6

[22] Aggressively scaled high-k gate dielectric with excellent performance and high temperature stability for 32nm and beyond [J].

Sivasubramani, P. ;

Kirsch, P. D. ;

Huang, J. ;

Park, C. ;

Tan, Y. N. ;

Gilmer, D. C. ;

Young, C. ;

Freeman, K. ;

Hussain, M. M. ;

Harris, R. ;

Song, S. C. ;

Heh, D. ;

Choi, R. ;

Majhi, P. ;

Bersuker, G. ;

Lysaght, P. ;

Lee, B. H. ;

Tseng, H. -H. ;

Jur, J. S. ;

Lichtenwalner, D. J. ;

Kingon, A. I. ;

Jammy, R. .

2007 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, VOLS 1 AND 2, 2007, :543-+

[23] Application of Advanced Atomic Layer Deposition for Understanding and Control of VTH and EOT in Metal/High-k Gate Stacks [J].

Toriumi, Akira ;

Nabatame, Toshihide ;

Ota, Hiroyuki .

ATOMIC LAYER DEPOSITION APPLICATIONS 4, 2008, 16 (04) :69-+

[24] Electrical observation of deep traps in high-k/metal gate stack transistors [J].

Harris, HR ;

Choi, R ;

Sim, JH ;

Young, CD ;

Majhi, P ;

Lee, BH ;

Bersuker, G .

IEEE ELECTRON DEVICE LETTERS, 2005, 26 (11) :839-841

[25] W versus Co-Al as Gate Fill-Metal for Aggressively Scaled Replacement High-k/Metal Gate Devices for (Sub-)22 nm Technology Nodes [J].

Veloso, Anabela ;

Chew, Soon Aik ;

Schram, Tom ;

Dekkers, Harold ;

Van Ammel, Annemie ;

Witters, Thomas ;

Tielens, Hilde ;

Heylen, Nancy ;

Devriendt, Katia ;

Sebaai, Farid ;

Brus, Stephan ;

Ragnarsson, Lars-Ake ;

Pantisano, Luigi ;

Eneman, Geert ;

Carbonell, Laure ;

Richard, Olivier ;

Favia, Paola ;

Geypen, Jef ;

Bender, Hugo ;

Higuchi, Yuichi ;

Phatak, Anup ;

Thean, Aaron ;

Horiguchi, Naoto .

JAPANESE JOURNAL OF APPLIED PHYSICS, 2013, 52 (04)

[26] Gate-Stack Engineering to Improve the Performance of 28 nm Low-Power High-K/Metal-Gate Device [J].

Park, Jeewon ;

Jang, Wansu ;

Shin, Changhwan .

MICROMACHINES, 2021, 12 (08)

[27] Gate Stack Process Optimization for TDDB Improvement in 28nm High-k/Metal Gate nMOSFETs [J].

Lee, Kyong Taek ;

Kim, Hyunjin ;

Park, Junekyun ;

Park, Jongwoo .

2012 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2012,

[28] Intrinsic Dielectric Stack Reliability of a High Performance Bulk Planar 20nm Replacement Gate High-K Metal Gate Technology and Comparison to 28nm Gate First High-K Metal Gate Process [J].

McMahon, W. ;

Tian, C. ;

Uppal, S. ;

Kothari, H. ;

Jin, M. ;

LaRosa, G. ;

Nigam, T. ;

Kerber, A. ;

Linder, B. P. ;

Cartier, E. ;

Lai, W. L. ;

Liu, Y. ;

Ramachandran, R. ;

Kwon, U. ;

Parameshwaran, B. ;

Krishnan, S. ;

Narayanan, V. .

2013 IEEE INTERNATIONAL RELIABILITY PHYSICS SYMPOSIUM (IRPS), 2013,

[29] Compatibility of dual metal gate electrodes with high-K dielectrics for CMOS [J].

Lee, J ;

Suh, YS ;

Lazar, H ;

Jha, R ;

Gurganus, J ;

Lin, YX ;

Misra, V .

2003 IEEE INTERNATIONAL ELECTRON DEVICES MEETING, TECHNICAL DIGEST, 2003, :323-326

[30] Dual work function high-k/metal gate CMOS FinFETs [J].

Hussain, Muhammad Mustafa ;

Smith, Casey ;

Kalra, Pankaj ;

Yang, Ji-Woon ;

Gebara, Gabe ;

Sassman, Barry ;

Kirsch, Paul ;

Majhi, Prashant ;

Song, Seung-Chul ;

Harris, Rusty ;

Tseng, Hsing -Huang ;

Jammy, Raj .

ESSDERC 2007: PROCEEDINGS OF THE 37TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2007, :207-+

← 1 2 3 4 5 →