A 100-Mhz Bandwidth 80-dB Dynamic Range Continuous-Time Delta-Sigma Modulator with a 2.4-Ghz Clock Rate

被引:2
|
作者
Xiao, Yao [1 ]
Lu, Zhifei [1 ]
Ren, Zhaofeng [1 ]
Peng, Xizhu [1 ]
Tang, He [1 ]
机构
[1] Univ Elect Sci & Technol China, SoC Design Ctr, Sch Elect Sci & Engn, Chengdu 610054, Peoples R China
来源
NANOSCALE RESEARCH LETTERS | 2020年 / 15卷 / 01期
关键词
Delta-sigma modulator; Wide-bandwidth; Nanoscale CMOS process; Continuous-time; SAMPLING PIPELINED ADC;
D O I
10.1186/s11671-020-3284-4
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
The bandwidth of a Delta sigma modulator is limited by the clock rate due to the oversampling ratio requirement. As the nanoscale CMOS processes are developing rapidly, it is possible to design wide bandwidth and high dynamic range continuous-time Delta sigma modulators for high-frequency applications. This paper proposes a 3rd-order 4-bit continuous-time Delta sigma modulator with a single-loop feedforward topology. This modulator is designed in a 40-nm CMOS process and achieves 80-dB dynamic range and a 100-MHz bandwidth at a clock rate of 2.4 GHz. The modulator consumes 69.7 mW from 1.2 V power supply.
引用
收藏
页数:8
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