SOPC architecture for a key point detector

被引：2

作者：

Chati, H. Djakou ^{[1
]}

Muehlbauer, F. ^{[1
]}

Braun, T. ^{[2
]}

Bobda, C. ^{[1
]}

Berns, K. ^{[2
]}

机构：

[1] Kaiserslautern Univ Technol, Self Organizing Embedded Syst Grp, Kaiserslautern, Germany

[2] Kaiserslautern Univ Technol, Robot Res Lab, Kaiserslautern, Germany

来源：

2007 INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE LOGIC AND APPLICATIONS, PROCEEDINGS, VOLS 1 AND 2 | 2007年

关键词：

D O I：

10.1109/FPL.2007.4380751

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

The design and implementing of a key point detector on embedded reconfigurable hardware is investigated. The major challenges are efficient hardware/software partitioning of the key point detector algorithm, data flow management as well as efficient use of memory, bus and processor. We present a modular and manual hardware/software co-design, with its implementation on a Xilinx XUP-Virtex II Pro board to solve these issues.

引用

页码：710 / 713

页数：4