New Design of 2 x VDD-Tolerant Power-Rail ESD Clamp Circuit for Mixed-Voltage I/O Buffers in 65-nm CMOS Technology

被引：13
|
作者：
Yeh, Chih-Ting [1 ,2 ]
Ker, Ming-Dou [1 ,3 ]
机构：
[1] Natl Chiao Tung Univ, Dept Elect Engn, Hsinchu 300, Taiwan
[2] Ind Technol Res Inst, Informat & Commun Res Labs, Hsinchu 310, Taiwan
[3] I Shou Univ, Dept Elect Engn, Kaohsiung 840, Taiwan
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2012年 / 59卷 / 03期
关键词：
Electrostatic discharge (ESD); holding voltage; mixed-voltage I/O buffers; power-rail ESD clamp circuit; PROTECTION DESIGN;
D O I：
10.1109/TCSII.2012.2184372
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A new 2 x VDD-tolerant power-rail electrostatic discharge (ESD) clamp circuit realized with only thin gate oxide 1-V (1 x VDD) devices and a silicon-controlled rectifier (SCR) as the main ESD clamp device has been proposed and verified in a 65-nm CMOS process. This new design has a low standby leakage current by reducing the voltage difference across the gate oxide of the devices in the ESD detection circuit. The proposed design with an SCR width of 50 mu m can achieve a 6.5-kV human-body-model ESD level, a 300-V machine-model ESD level, and a low standby leakage current of only 103.7 nA at room temperature under the normal circuit operating condition with 1.8 V bias.
引用
收藏
页码：178 / 182
页数：5
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