Design of a High Speed CMOS Image Sensor with a Hybrid Single-Slope Column ADC and a Finite State Machine

被引：0

作者：

Park, Keunyeol ^{[1
]}

Jin, Minhyun ^{[1
]}

Kim, Soo Youn ^{[1
]}

Song, Minkyu ^{[1
]}

机构：

[1] Dongguk Univ, Dept Semicond Sci, Seoul, South Korea

来源：

PROCEEDINGS INTERNATIONAL SOC DESIGN CONFERENCE 2017 (ISOCC 2017) | 2017年

关键词：

CMOS image sensor; hybrid single-slope column ADC; sampling capacitor; single ramp generator; 4-input comparator; finite state machine;

D O I：

暂无

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

In this paper, design of a CMOS Image sensor (CIS) with a hybrid single-slope ADC is presented. To obtain a small size and a high conversion rate CIS, no sampling capacitor structure is employed. This is implemented with a DC reference voltage and a single ramp generator. Further, by changing the input node of comparator, it reduces gain errors generated by a conventional 4-input comparator's differentia pair. The proposed hybrid ADC selects the resistor DAC's reference voltage controlled by a Finite State Machine(FSM), and converts the residual voltage with the single slope technique. Based on 1-Poly 5-Metal 90nm back side illuminated(BSI) CIS process, the chip satisfies 1920 x 1440 pixel resolution whose pitch is 1.4um and 1.75-Tr active pixel sensor(APS).

引用

页码：95 / 96

页数：2

共 4 条

[1]

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[2]

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[3]

Sugiki T., 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056), P108, DOI 10.1109/ISSCC.2000.839712

[4] A 1/1.8-inch 6.4-MPixel 60 frames/s CMOS image sensor with seamless mode change [J].

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Inada, Yoshiaki ;

Kuramochi, Souichiro ;

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Tajima, Akari ;

Nakajima, Tadashi ;

Kudoh, Yoshiharu ;

Koga, Fumihiko ;

Kasagi, Yasuo ;

Watanabe, Shinya ;

Nomoto, Tetsuo .

IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2006, 41 (12) :2998-3006

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