Circuit design and verification with Esterel v7 and esterel studio

被引：5

作者：

Berry, Gerard ^{[1
]}

机构：

[1] Coll France, Esterel Technol, Paris, France

来源：

2007 IEEE INTERNATIONAL HIGH LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2007年

关键词：

D O I：

10.1109/HLDVT.2007.4392800

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

引用

页码：133 / 136

页数：4

共 11 条

[1]

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[2]

ARDITI L, 2004, FMCAD 04 AUSTR TEX

[3]

BERRY G, 2003, P ICCAD 03 SAN JOS C

[4]

BERRY G, 1998, ESTEREL V5 91 PRIMER

[5]

Berry Gerard, 1999, The constructive semantics of pure Esterel.

[6]

*EST TECHN, EST V7 LANG REF MAN

[7]

FILLINGER M, 2007, P SAME 07 FOR SOPH A

[8] STATECHARTS - A VISUAL FORMALISM FOR COMPLEX-SYSTEMS [J].

HAREL, D .

[9]

Potop-Butucaru Dumitru, 2007, Compiling Esterel, P79

Schneider, K .

SECOND INTERNATIONAL CONFERENCE ON APPLICATION OF CONCURRENCY TO SYSTEMS DESIGN, PROCEEDINGS, 2001, :143-154