Variability aware timing models at the standard cell level

Standard cell timing variations are caused by process non-idealities that are not traditionally captured within standard timing characterization tools. This paper presents two approaches to creating variability aware standard cell timing models in the presence of lithographic variations. The first approach uses circuit simulation of rectangular transistors to create delay sensitivity tables to transistor length and transistor width for each cell. The second approach utilizes lithography contours to characterize cell performance. The contour based approach is used to characterize two standard cells in the presence of active and poly layer focus exposure variations, misalignment, and layout proximity effects. The delay response to focus and exposure exhibits Bossung-like delay behavior and can be fit with a compact parameter delay model. Both approaches lead to the creation of variability aware timing models in the form of delay variability tables or compact parameter timing models. These models enable static timing analysis tools to perform critical path variability aware delay analysis using a presumed layout-dependent distribution of process parameters with little expense in runtime.