Reduction of Gate-Induced Drain Leakage Current of Polycrystalline Silicon Thin-Film Transistor by Drain Bias Sweeping

Method of drain bias sweeping is reported to reduce the gate-induced drain leakage (GIDL) current but with other electrical parameters unaffected for p-type polycrystalline silicon thin-film transistors. It is proposed to be due to local electron trapping in the gate oxide near the drain after drain-bias sweeping such that the gate bias effect is screened. The effects of drain bias sweeping can be achieved equivalently by a DC bias stress. It is further proposed that pulsed drain bias sweeping is a most reliable method to achieve suppressed GIDL current and unaffected subthreshold and on-state characteristics.