Hierarchical test access architecture for embedded cores in an integrated circuit

The rapid emergence of reusable core-based designs, in the last few years, poses new challenges to the IEEE test access standard 1149.1 [1,4]. Due to widespread industrial acceptance of 1149.1 standard, IC's are now expected to be 1149.1-compliant. At the same time, a typical IC, like the TMS470 microcontroller manufactured by TI, often contains multiple cores with built-in 1149.1-compliant Test Access Port (TAP), as well as significant amounts of non-core logic, which does not have any built-in test access mechanism. In this paper, we present a new TAP design that enables systematic integration of TAP'ed cores with non-TAP'ed logic, and makes the total IC 1149.1 compliant, at the same time. This TAP design, designated Hierarchical Test Access Port (HTAP), has exactly the same I/O pin specifications as an 1149.1-compliant TAP, and can either serve as an 1149.1-compliant TAP, or act as an arbitrator between existing TAPs in the embedded cores. Behavior of the HTAP-whether to act as a TAP or as an arbitrator of TAPs-is controlled via the TMS input pin.