This paper attempts to discusses wholly the places where the problems take place easily in VHDL design. It includes the following aspects. The difference between signal and variable, the sphere of action and the characteristic of time delay; The sensitivity quantum during the process, the position of clock, the advantage of trying to use one clock, Besides simple design, it is often impossible to make all functions with a process, so multi-process is used extensively in designing program in VHDL, it is very helpful to understand the advantages and disadvantages of multi-process in design of complicated VHDL; The cause of glitch signal and how to clear it up, how to avoid the problem of glitch signal producing; Combinational logic circuit and sequential logic circuit, The relation between clock and synchronous circuit & asynchronous circuit, the difference between synchronous set and asynchronous set, try to use synchronous circuit and synchronous set; The touching off the way of Latch and Flip-flop; How to make best use of the resource library and the accurate way of expressing operands in order to achieve the perfect program structure and correct operation result, The necessity of introducing tristate gate and its usage; The relation between VHDL and NIOS embed processor & modem DSP Combining my experience, some specific problem have been explained and my own view t have been put forward, hoping to be useful and helpful to VHDL designers.
