A fully integrated CMOS phase-locked loop with 30 MHz to 2 GHz locking range and ±35 ps jitter

被引：2

作者：

Xu, C ^{[1
]}

Sargeant, W ^{[1
]}

Laker, KR ^{[1
]}

van der Spiegel, J ^{[1
]}

机构：

[1] Univ Penn, Dept Elect Engn, Philadelphia, PA 19104 USA

来源：

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING | 2003年 / 36卷 / 1-2期

关键词：

phase-locked loop (PLL); clock data recovery; dual loop architecture; jitter;

D O I：

10.1023/A:1024410016948

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

A fully integrated phase-locked loop (PLL) fabricated in a 0.24 mum, 2.5 v digital CMOS technology is described. The PLL is intended for use in multi-gigabit-per-second clock recovery circuits in fiber-optic communication chips. This PLL first time achieved a very large locking range measured to be from 30 MHz up to 2 GHz in 0.24 mum CMOS technologies. Also it has very low peak-to-peak jitter less than +/-35 ps at 1.25 GHz output frequency.

引用

页码：91 / 97

页数：7

共 41 条

[1] A Fully Integrated CMOS Phase-Locked Loop with 30 MHz to 2 GHz Locking Range and ±35 ps Jitter
Chao Xu
Winslow Sargeant
Kenneth R. Laker
Jan Van der Spiegel
Analog Integrated Circuits and Signal Processing, 2003, 36 : 91 - 97
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