High-Resolution Waveform Capture Device on a Cyclone-V FPGA

被引:6
作者
Charlot, Noeloikeau F. [1 ]
Gauthier, Daniel J. [1 ]
Pomerance, Andrew [2 ]
机构
[1] Ohio State Univ, Dept Phys, Columbus, OH 43202 USA
[2] Potomac Res LLC, Alexandria, VA 22311 USA
关键词
Field programmable gate arrays; Transmission line measurements; Registers; Calibration; Clocks; Power transmission lines; Phase locked loops; Time-to-digital converter (TDC); digital storage oscilloscope (DSO); field programmable gate array (FPGA); phase lock loop (PLL); dynamic phase shift (DPS); carry chain (CC); TO-DIGITAL CONVERTER;
D O I
10.1109/ACCESS.2021.3123277
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
We introduce the waveform capture device (WCD), a flexible measurement system capable of recording complex digital signals on trillionth-of-a-second (ps) time scales. The WCD is implemented via modular code on an off-the-shelf field-programmable gate-array (FPGA, Intel/Altera Cyclone V), and incorporates both time-to-digital converter (TDC) and digital storage oscilloscope (DSO) functionality. The device captures a waveform by taking snapshots of a signal as it propagates down an ultra-fast transmission line known as a carry chain (CC). It is calibrated via a novel dynamic phase-shifting (DPS) method that requires substantially less data and resources than the state-of-the-art. Using DPS, we find the measurement resolution - or mean propagation delay from one CC element to the next - to be 4.91 +/- 0.04 ps (4.54 +/- 0.02 ps) for a pulse of logic high (low). Similarly, we find the single-shot precision - or mean error on the timing of the waveform - to be 29.52 ps (27.14 ps) for pulses of logic high (low). We verify these findings by reproducing commercial oscilloscope measurements of asynchronous ring-oscillators on FPGAs, finding the mean pulse width to be 0.240 +/- 0.002 ns per inverter gate. Finally, we present a careful analysis of design constraints, introduce a novel error correction algorithm, and sketch a simple extension to the analog domain. We also provide the Verilog code instantiating our design's hardware primitives in an Appendix, and make our FPGA interfacing methods available as an open-source Python library at https://github.com/Noeloikeau/fpyga.
引用
收藏
页码:146203 / 146213
页数:11
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