Steep-subthreshold slope dual gate negative capacitance junction less FET with dead channel: TCAD approach for digital/RF applications

In pursuit of lowering power densities and reducing energy efficiency constraints, execution grid of arising electronic devices are being investigated to track down alternative options for MOSFETs. Herein we present and examine a new structural plan technique for double gate junction less FET (DG - JLFET), which conveys benefits in all fronts of design, performance, and fabrication perspectives. This proposed structure is called dead channel double gate junction less FET (DC-DGJLFET). The dead channel means absence of conducting charge carriers in the mid of channel in the device due to presence of P-type layer which virtually reduces effective tSi and improve FOMs of the device. The performance metrics of DC-DGJLFET is compared with negative capacitance DCDGJLFET designed on the same technology node. Also variability issues found in baseline transistors can be overcomed by incorporating the ferroelectric layer in the FET. The proposed NCFET is also compared with the IRDS requirements for various FOMs.