Study on random telegraph noise of high-idmetal-gate gate-all-around poly-Si nanowire transistors

被引：0

作者：

Chang, You-Tai ^{[1
]}

Tsai, Yueh-Lin ^{[1
]}

Peng, Kang-Ping ^{[1
]}

Su, Chun-Jung ^{[2
]}

Li, Pei-Wen ^{[1
]}

Lin, Horng-Chih ^{[1
]}

机构：

[1] Natl Chiao Tung Univ, Dept Elect Engn & Inst, 1001 Daxue Rd, Hsinchu, Taiwan

[2] Taiwan Semicond Res Inst, 26 Prosper Rd 1,Hsinchu Sci Pk, Hsinchu, Taiwan

来源：

JAPANESE JOURNAL OF APPLIED PHYSICS | 2020年 / 59卷 / SG期

关键词：

SILICON; FINFET; LAYERS; TRAPS;

D O I：

10.7567/1347-4065/ab5b67

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

In this Paper, we investigated random telegraph noise (RTN) characteristics of gate-all-around poly-Si nanowire (NW) transistors with high-kappa oxide/metal-gate (HK/MG) stack. Distinct two-level RTN signals were measured on NW transistors with effective channel length of 150 nm and channel width of 30 nm. Values of time constants for charge emission from and capture by traps were extracted from measured RTN signals We proposed a new theoretical scheme to evaluate the location and energy level of the corresponding trap. The trap was assessed to be present within the interfacial layer (IL) at a spatial location approximate 1 nm away from the IL/channel interface and 68 nm in proximity to the source side. (C) 2020 The Japan Society of Applied Physics

引用

页数：5

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