PSRR-enhanced low-dropout regulator

被引：4
作者：
Huang, W. -J. [1 ,2 ]
Liu, S. -I. [1 ,2 ]
机构：
[1] Natl Taiwan Univ, Grad Inst Elect Engn, Taipei 10764, Taiwan
[2] Natl Taiwan Univ, Dept Elect Engn, Taipei 10764, Taiwan
来源：
ELECTRONICS LETTERS | 2011年 / 47卷 / 01期
关键词：
COMPENSATION;
D O I：
10.1049/el.2010.2869
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A power supply rejection ratio (PSRR) enhancement technique for the low-dropout regulator (LDR) is presented. This proposed LDR with a bandgap reference has been fabricated in a 0.35 mu m CMOS process, and its active chip area is 0.1978 mm(2). From experimental results, the proposed LDR provides a stable output voltage without the output capacitor and achieves over a PSRR of 276 dB at 100 kHz for the output current within 0-150 mA. In addition, the output integrated noise is 21.45 mu V(rms) within a frequency between 22 Hz and 80 kHz.
引用
收藏
页码：17 / U32
页数：2
相关论文
共 5 条
[1]  
Allen PhillipE., 2002, CMOS ANALOG CIRCUIT, V2nd
[2]  
Gupta Vishal., 2007, 2007 IEEE International Solid-State Circuits Conference ISSCC, P520, DOI [10.1109/ISSCC.2007.373523, DOI 10.1109/ISSCC.2007.373523]
[3]  
Hoon SK, 2005, IEEE CUST INTEGR CIR, P759
[4]   Capacitor-free low dropout regulators using nested Miller compensation with active resistor and 1-bit programmable capacitor array [J].
Huang, W. -J. ;
Liu, S. -I. .
IET CIRCUITS DEVICES & SYSTEMS, 2008, 2 (03) :306-316
[5]   A capacitor-free CMOS low-dropout regulator with damping-factor-control frequency compensation [J].
Leung, KN ;
Mok, PKT .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2003, 38 (10) :1691-1702
1