Dead-Time and Semiconductor Voltage Drop Compensation for Cascaded H-Bridge Converters

被引：37

作者：

Mora, Andres ^{[1
]}

Juliet, Jorge ^{[1
]}

Santander, Alex ^{[2
]}

Lezana, Pablo ^{[1
]}

机构：

[1] Univ Tecn Federico Santa Maria, Dept Elect Engn, Valparaiso 2390123, Chile

[2] CDEC SING, Direct Planning & Dev, Santiago 7580125, Chile

来源：

IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS | 2016年 / 63卷 / 12期

关键词：

Cascaded H-bridges (CHBs); dead-time; multilevel converters; semiconductor voltage drop; PWM INVERTERS; MULTILEVEL; SCHEME; STRATEGY; IMPACT;

D O I：

10.1109/TIE.2016.2563378

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Compensation of nonlinear effects generated by dead-time and semiconductors voltage drop has been widely studied in the literature about two-level converters. This paper takes a closer look at those analyses for multi-level converters, specifically for a cascaded H-bridge (CHB) converter modulated with phase-shifted pulse width modulation. The interaction between the cells is analyzed for a generic n-cell converter, from which a general expression for the distortion generated by the nonlinearities has been obtained. Based on this expression, a compensation signal for the overall converter is calculated on each sample time, which is a fraction of the triangular carrier used to modulate each cell, thus significantly improving the quality of the output voltage signals. Experimental validation of the proposed compensation method is presented using a three-phase four-cell CHB converter prototype of 5.5 kW.

引用

页码：7833 / 7842

页数：10

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