AEthereal network on chip: Concepts, architectures, and implementations

被引：438
作者：
Goossens, K [1 ]
Dielissen, J [1 ]
Radulescu, A [1 ]
机构：
[1] Philips Res Labs, NL-5656 AA Eindhoven, Netherlands
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2005年 / 22卷 / 05期
关键词：
D O I：
10.1109/MDT.2005.99
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
Many SoC applications require guaranteed levels of service and performance. Can networks on chips ( NoCs) enable such guarantees? Here, the authors demonstrate that the AEthereal network can. This particular NoC, developed at Philips Research Laboratories, encompasses hardware, a programming model, and a design flow. Read on to find out about the details.
引用
收藏
页码：414 / 421
页数：8
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