An Efficient FPGA-Based Parallel Phase Unwrapping Hardware Architecture

This paper presents a novel phase unwrapping hardware architecture for imaging applications. The architecture is a hardware implementation of a path-independent noniterative discrete cosine transform (DCT) based minimum mean square algorithm for accurate and fast phase unwrapping. The implementation is based on field programmable gate array. The architecture is able to exploit the parallelism among different stages of the algorithm for maximizing the throughput of the computation. A network-on-chip platform is built for the computation time measurement. As compared with other implementations for fast phase unwrapping, the proposed architecture has the advantages of high throughput, high accuracy, and low power consumption.