Design and analysis of ultra-low power 18T adaptive data track flip-flop for high-speed application

This paper proposes a novel master slave (MS) flip-flop design achieved by using only 18 transistors with a single-phase clock and mixed topology. This design has lowest complexity, so flip-flop basically focuses on the performance issue such as delay (T-CQ) and average power consumption and compared with the other existing logic structured flip-flops. The proposed circuit is implemented at 65-nm Complementary Metal-Oxide Semiconductor (CMOS), and 18-nm finFET technology node using cadence virtuoso. The proposed flip-flop architecture have outperformed transmission gate flip-flop (TGFF) in terms of power (i.e., 74.52%). It is also showing improvement in terms of power as compared to 18-transistor single-phase clocking (18TSPC). This work also enhances the speed by reducing the delay minimum of 11.28% and PDP minimum of 37.18%. By using adaptive pass transistors topology to construct flip-flop, the total area of the proposed flip-flop reduces by a minimum of 4.78% with respect to 18TSPC, and also with the other flip-flops reported in this paper. The proposed circuit can work properly within the frequency range up to 2-GHz clock frequency. Monte Carlo simulations of Power and C to Q delay have been performed for 1000 samples.