A Low-Voltage PLL Design Using a New Calibration Technique for Low-Power Implantable Biomedical Systems

This paper describes a low-voltage phase-locked loop (PLL) design using a new calibration technique for low-power implantable biomedical systems. The proposed PLL uses a switching technique in the charge pump and a bulk-driven technique in the voltage-controlled oscillator (VCO) to reduce power consumption and operate at ultralow voltage. To compensate for the process variation, a calibration circuit is proposed to control the capacitor array of the VCO. This work was implemented in a 0.18-mu m standard CMOS process with a 1.8-V supply voltage. The results show that the proposed PLL can operate from 402 to 405 MHz with a 0.7-V power supply and provides ten channel spaces for switching (where every channel has a bandwidth of 300 KHz) for biomedical system applications. At 405 MHz, the measured phase noise and reference spurs are -99.49 dBc/Hz at 1 MHz offset and -48.04 dBc, respectively. Furthermore, the measured root-mean-square jitter and peak-to-peak jitter are 9.93 and 82.03 ps, respectively. The total power consumption of the PLL is only 0.425 mW, and the active die area is 0.067 mm(2).