Low voltage/low power sub 50 nm double gate SOI ratioed logic

被引：0

作者：

Mitra, S ^{[1
]}

Salman, A ^{[1
]}

Ioannou, DP ^{[1
]}

Tretz, C ^{[1
]}

Ioannou, DE ^{[1
]}

机构：

[1] George Mason Univ, ECE Dept, Fairfax, VA 22030 USA

来源：

2003 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS | 2003年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：177 / 178

页数：2

共 3 条

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[2] Mitra S, 2002, 2002 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, P66, DOI 10.1109/SOI.2002.1044419
[3] Two gates are better than one - A planar self-aligned double-gate MOSFET technology to achieve the best on/off switching ratios as gate lengths shrink
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Sicina, RM
Benedict, J
Wong, HSP
[J]. IEEE CIRCUITS & DEVICES, 2003, 19 (01): : 48 - 62