A 512-Gb 3-b/Cell 64-Stacked WL 3-D-NAND Flash Memory

被引：86

作者：

Kim, Chulbum ^{[1
]}

Kim, Doo-Hyun ^{[1
]}

Jeong, Woopyo ^{[1
]}

Kim, Hyun-Jin ^{[1
]}

Park, Il Han ^{[1
]}

Park, Hyun-Wook ^{[1
]}

Lee, JongHoon ^{[1
]}

Park, JiYoon ^{[1
]}

Ahn, Yang-Lo ^{[1
]}

Lee, Ji Young ^{[1
]}

Kim, Seung-Bum ^{[1
]}

Yoon, Hyunjun ^{[1
]}

Yu, Jae Doeg ^{[1
]}

Choi, Nayoung ^{[1
]}

Kim, NaHyun ^{[1
]}

Jang, Hwajun ^{[1
]}

Park, JongHoon ^{[1
]}

Song, Seunghwan ^{[1
]}

Park, YongHa ^{[1
]}

Bang, Jinbae ^{[1
]}

Hong, Sanggi ^{[1
]}

Choi, Youngdon ^{[1
]}

Kim, Moo-Sung ^{[1
]}

Kim, Hyunggon ^{[1
]}

Kwak, Pansuk ^{[1
]}

Ihm, Jeong-Don ^{[1
]}

Byeon, Dae Seok ^{[1
]}

Lee, Jin-Yub ^{[1
]}

Park, Ki-Tae ^{[1
]}

Kyung, Kye-Hyun ^{[1
]}

机构：

[1] Samsung Elect Co Ltd, Flash Prod & Technol, Memory Business, Hwaseong 445701, South Korea

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2018年 / 53卷 / 01期

关键词：

3-bit per cell; 3-D NAND; 64 word-line(WL) stack; cache program; error correction; NAND flash memory; reliability; self IO test; V-NAND;

D O I：

10.1109/JSSC.2017.2731813

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A 64-word-line-stacked 512-Gb 3-b/cell 3-D NAND flash memory is presented. After briefly examining the challenges that occur to a stack, several technologies are suggested to resolve the issues. For performance enhancement, a novel program method hiding two-page data loading time is presented. This paper also discusses an electrical annealing improving reliability characteristic by removing holes in shallow traps. In addition, a valley tracking read for reducing timing overhead at a read retry is introduced by fast finding optimal read levels. Finally, a high-speed self-test mode for IO operation is presented. The chip, designed with the fourth generation of V-NAND technology, achieved an areal density of 3.98 Gb/mm(2) and operated up to 1 Gb/s at 1.2 V.

引用

页码：124 / 133

页数：10

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