A 50.1-Mpixel 14-Bit 250-frames/s Back-Illuminated Stacked CMOS Image Sensor With Column-Parallel kT/C-Canceling S&H and &UDELTA;ΣADC

被引：7

作者：

Okada, Chihiro ^{[1
]}

Zeituni, Golan ^{[1
]}

Uemura, Koushi ^{[1
]}

Hung, Luong ^{[1
]}

Matsuura, Kouji ^{[1
]}

Moue, Takashi ^{[1
]}

Kodama, Kazutoshi ^{[1
]}

Okano, Masafumi ^{[1
]}

Morikawa, Takafumi ^{[1
]}

Yamashita, Kazuyoshi ^{[1
]}

Oka, Osamu ^{[1
]}

Inada, Yoshiaki ^{[1
]}

Shvartz, Itai ^{[1
]}

Ben Shem, Ariel ^{[1
]}

Eshel, Noam ^{[1
]}

机构：

[1] Sony Semicond Solut Corp, Atsugi, Kanagawa 2430014, Japan

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2021年 / 56卷 / 11期

关键词：

Analog-to-digital converter (ADC); CMOS image sensor; high frame rate; high resolution; large optical format; low noise; low power;

D O I：

10.1109/JSSC.2021.3111154

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This article presents a 50.1-Mpixel 14-bit 250-frames/s back-illuminated stacked CMOS image sensor on 35-mm optical format exhibiting 1.18-e(-)rms random noise at 0 dB. This sensor employs a load reduction technique by splitting half of pixel signal line using a Cu-Cu connection technology underneath the pixel area, pipelined operation with a gain-adaptive column-parallel kT/ C noise-canceling sample and hold, and a 250-frames/s scanning rate and 14-bit resolution delta-sigma analog-to-digital converter (ADC) circuit. Moreover, an on-chip online calibration of column mismatch maintains the non-linearity of the output image within -0.42%. As a result, FoM6 (e(-)* pJ/step) of 0.09 is obtained as the state-of-the-art performance.

引用

页码：3228 / 3235

页数：8

共 21 条

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