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- [23] Timing Generator Using Dual Delay-Locked Loop 2009 IEEE NUCLEAR SCIENCE SYMPOSIUM CONFERENCE RECORD, VOLS 1-5, 2009, : 428 - 430
- [25] A Low-Jitter All-Digital Phase-Locked Loop Using a Suppressive Digital Loop Filter 2009 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION AND TEST (VLSI-DAT), PROCEEDINGS OF TECHNICAL PROGRAM, 2009, : 158 - 161
- [28] A Low-Jitter Self-Biased Phase-Locked Loop for SerDes 2016 INTERNATIONAL SOC DESIGN CONFERENCE (ISOCC), 2016, : 59 - 60
- [29] Design of delay-locked loop (DLL) with low jitter and high lose lock time in UWB-IR system 2006 ASIA-PACIFIC CONFERENCE ON COMMUNICATION, VOLS 1 AND 2, 2006, : 796 - +