The decoder of trellis code implemented by CMOS analog circuits

被引：0
|
作者：
Yang, Shuhui [1 ]
Li, Denghua [1 ]
Qiu, Yulin [2 ]
机构：
[1] Beijing Informat S&T Univ, Dept Info & Comm, Beijing 100101, Peoples R China
[2] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China
来源：
ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年
基金：
中国国家自然科学基金;
关键词：
analog decoder; trellis-code; probability decoding; turbo code; CMOS;
D O I：
10.1109/ICASIC.2007.4415776
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper analyses some circuits of the analog decoder of (5,2,3) trellis code, which is implemented by CMOS analog circuits. The decoding performance of the analog decoder is given. Simulation results show that the analog decoder decreases at least one decimal power consumption and chip area at the same bit rate, compared with the digital decoder. For the Turbo code and LDPC, if they are decoded by digital circuits, the quantity of the transistors and the computing power will be very great. If we use analog decoder, the power consumption and the chip area will be very small.
引用
收藏
页码：898 / 901
页数：4
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