TSV-OCT: A Scalable Online Multiple-TSV Defects Localization for Real-Time 3-D-IC Systems

被引:16
作者
Dang, Khanh N. [1 ,2 ]
Ahmed, Akram Ben [3 ]
Abdallah, Abderazek Ben [2 ]
Tran, Xuan-Tu [1 ]
机构
[1] Vietnam Natl Univ, VNU Univ Engn & Technol, VNU Key Lab Smart Integrated Syst SISLAB, Hanoi 123106, Vietnam
[2] Univ Aizu, Grad Sch Comp Sci & Engn, Adapt Syst Lab, Aizu Wakamatsu, Fukushima 9658580, Japan
[3] Keio Univ, Dept Informat & Comp Sci, Yokohama, Kanagawa 2238522, Japan
关键词
Through-silicon vias; Built-in self-test; Time factors; Task analysis; Fault tolerance; Fault tolerant systems; Error correction code (ECC); fault localization; fault tolerance; through-silicon via (TSV); product code; FAULT-TOLERANT ARCHITECTURE; THROUGH-SILICON; PRODUCT CODES; DESIGN; CIRCUITS; EFFICIENT; REPAIR;
D O I
10.1109/TVLSI.2019.2948878
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
In order to detect and localize through-silicon-via (TSV) failures in both manufacturing and operating phases, most of the existing methods use a dedicated testing mechanism with long response time and prerequisite interruptions for online testing. This article presents an error correction code (ECC)-based method named "TSV on-communication test" (TSV-OCT) to detect and localize faults without halting the operation of TSV-based 3-D-IC systems. We first propose a statistical detector, a method to detect open and short defects in TSVs that work in parallel with data transactions. Second, we propose an isolation-and-check algorithm to enhance the localization ability of the method. Moreover, the Monte Carlo simulations show that the proposed statistical detector increases $\times 2$ the number of detected faults when compared to conventional ECC-based techniques. With the help of isolation and check, TSV-OCT localizes the number of defects up to $\times 4$ and $\times 5$ higher. In addition, the response time is kept below 65 000 cycles, which could be easily integrated into real-time applications. On the other hand, an implementation of TSV-OCT on a 3-D Network-on-Chip (NoC) router shows no performance degradation for testing while having a reasonable area overhead.
引用
收藏
页码:672 / 685
页数:14
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