A Hybrid DMR latch to tolerate MNU using TDICE and WDICE

被引：5

作者：

Huang, Zhengfeng ^{[1
]}

Zhang, Yangyang ^{[1
]}

Su, Zian ^{[1
]}

Liang, Huaguo ^{[1
]}

Yao, Huijie ^{[1
]}

Ni, Tianming ^{[1
]}

机构：

[1] Hefei Univ Technol, Sch Elect Sci & Appl Phys, Hefei 230009, Anhui, Peoples R China

来源：

2018 IEEE 27TH ASIAN TEST SYMPOSIUM (ATS) | 2018年

关键词：

Multiple Node Upsets; tolerance ability; mitigation; high impedance state; soft error; SINGLE-EVENT; DESIGN;

D O I：

10.1109/ATS.2018.00033

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

With technology scaling, nanoscale CMOS becomes more sensitive to Multiple Node Upsets (MNUs). This paper presents a Multiple Node Upsets Tolerant Hardened Latch based on hybrid Double Modular Redundancy. The proposed latch consists of two elementary cells derived from DICE: one cell is referred to as TDICE cell with four additional NMOS transistors in the feedback lines, the other cell is referred to as WDICE cell with two additional NMOS transistors and two additional PMOS transistors in the feedback lines. Additional transistors in the feedback line of DICE cell improves the resilience to multiple-node upset. Extensive simulation results show the proposed latch can tolerate the DNU with the probability of 100%, and tolerate the TNU with the probability of 95.70%. Also the proposed latch can make a good tradeoff among area, delay, power and robustness.

引用

页码：121 / 126

页数：6

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