Design and optimization of a hot-carrier resistant high-voltage nMOS transistor

被引：8
作者：
Annese, M [1 ]
Carniello, S [1 ]
Manzini, S [1 ]
机构：
[1] STMicroelect, TPA Grp, I-20010 Milan, Italy
来源：
IEEE TRANSACTIONS ON ELECTRON DEVICES | 2005年 / 52卷 / 07期
关键词：
hot carrier injection; high-voltage field-effect transistor (FET);
D O I：
10.1109/TED.2005.850625
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The hot-carrier degradation behavior of a class of high-voltage n-channel drift MOS transistors is experimentally investigated as a function of the geometrical (layout) parameters of the devices. The design restrictions, imposed by reliability requirements, are described as a subset of the space of the geometrical parameters (safe volume) which guarantees a safe hot-carrier operation. The optimization of the specific drain/source on-state resistance of the devices within the safe volume is discussed.
引用
收藏
页码：1634 / 1639
页数：6
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