Evolving magneto-electric device technologies

被引:16
作者
Sharma, N. [1 ]
Bird, J. P. [2 ]
Binek, Ch [3 ]
Dowben, P. A. [3 ]
Nikonov, D. [4 ]
Marshall, A. [1 ]
机构
[1] Univ Texas Dallas, Erik Johnson Sch Engn & Comp Sci, Richardson, TX 75080 USA
[2] Univ Buffalo, Dept Elect Engn, 230 Davis Hall, Buffalo, NY 14260 USA
[3] Univ Nebraska, Dept Phys & Astron, Jorgensen Hall, Lincoln, NE 68588 USA
[4] Intel Corp, MS RA3-252,2501 NW Century Blvd, Hillsboro, OR 97124 USA
基金
美国国家科学基金会;
关键词
beyond-complementary metal-oxide-semiconductor; complementary metal-oxide-semiconductor; spintronics; magneto-electric magnetic tunnel junction; magneto-electric field effect transistor; logic; full-adder; Verilog-A; BENCHMARKING; PERFORMANCE; MULTIFERROICS; METHODOLOGY; TRANSISTORS; GRAPHENE; PHYSICS;
D O I
10.1088/1361-6641/ab8438
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Here, several classes of magneto-electric devices, and their possible implementations as complementary metal-oxide-semiconductor (CMOS) replacements, are discussed. We consider how these devices can provide considerable improvements in functionality over CMOS when employed in novel circuit architectures. In the context of the magneto-electric device technologies discussed here, we detail the expansion of benchmarking into some of the newer beyond-CMOS technologies. This has required circuit level simulations, using Cadence Spectre or Spice, and Verilog-A based models of the magneto-electric magnetic tunnel junction devices have been used for circuit validation. This has been done as part of a global effort to develop comparative benchmarking standards across logic families, even as new benchmarking methodologies are being developed, while maintaining the familiar CMOS benchmarks.
引用
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页数:22
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